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preliminary w62410 dsp controller for tad publication release date: april 2000 - 1 - revision a1 general description the w62410 chip is a digital speech signal processor. the w62410 implements the streamtalk ? speech compression, voice prompt processing, telephone line signal processing, aflash and dram memory management and 16 i/o lines all in one chip for a fully digital answering machine. the w62410 acts as a slave processor to its host. the w62410 can be driven through a serial bus or an 8 bit parallel bus allowing the possibility for both 4 bit and 8 bit micro controllers to be used. since the w62410 is a slave to the host, the host is responsible for activating and deactivating all the functions the w62410 provides. features ? 24.576 mips for chipset core and 24.576 mhz crystal used. ? internal voice prompt rom, 16k 16 (256 kbits), which can be optionally swapped to an external winbond proprietary serial otp message storage option. ? support for up to four times 1m 4 or one 4m 4 types dram for up to 16 mbits storage space and refresh ability. ? support for up to four times samsung km29n040t, 512k 8, nand flash for up to 16 mbits of storage space. ? support for up to four times samsung km29n1600t, 2m 8, nand flash for up to 64 mbits of storage space. ? serial or 8-bits parallel c interface supported. ? one codec interface ( law codec such as the tp3054). ? sixteen available i/o lines. individually programmable as an input or output line. ? no external sram needed. ? real time clock supports weekday/hour/minute. ? the rtc keeps running while in power down mode (using a 32.768 khz crystal). ? low power consumption and power down mode support. ? fully static design. ? packaged in 100-pin pqfp
preliminary w62410 - 2 - pin configuration the w62410 is available in a 100 pin pqfp package. 2 1 3456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 v s s 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 o s c i n o s c o p v s s w r p i o 0 v d d /hostp8 /dtsext /reset /pwdn testb testa vdd vss /pllbypass clkin clkop vdd vss sclk rfs tfs dt dr irqex # ma11 sysclk e p p o 0 # / r a s e p s i o # / c a s 0 0 e p s i o # / c a s 1 1 e p s i o # / c a s 2 2 e p s i o # / c a s 3 3 / e p w r # / m w r / e p r d # / m r d e p p o 1 # m a 0 e p p o 2 # m a 1 e p p o 3 # m a 2 e p p o 4 # m a 3 e p p o 5 # m a 4 e p p o 6 # m a 5 e p p o 7 # m a 6 v d d e p d a t a m a 7 # 4 e p d a t a m a 8 # 5 e p d a t a m a 9 # 6 e p d a t a m a 1 # 7 0 e p d a t a m d 0 # 0 e p d a t a m d 1 # 1 e p d a t a m d 2 # 2 e p d a t a m d 3 # 3 / d a c k / b y t e h l d 0 v d d d1 /hprd /hpwr d 2 d 3 d4 d5 d6 d7 v s s d a t a0 d a t a1 d a t a2 d a t a3 d a t a4 d a t a5 d a t a6 d a t a7 d a t a8 vd d d a t a 9 d a t a 1 0 d a t a 1 1 d a t a 1 2 d a t a 1 3 d a t a 1 4 d a t a 1 5 4 x f t p d a t a o r d p i o 1 i o 2 i o 3 i o 4 i o 5 i o 6 i o 7 i o 8 i o 9 i o 1 i o 1 i o 1 i o 1 0 1 2 3 4 5 i o 1 i o 1 v s s w62410
preliminary w62410 publication release date: april 2000 - 3 - revision a1 block diagram example tad application the figure below shows the basic block diagram for building a digital answering machine using the w62410 chipset. in addition to the chipset the following are needed: ? a law codec. ? dram of flash for use as external memory storage space. ? a 4 or 8-bit controller (using the serial port or 8-bit parallel port of the chipset). ? a 24.576 mhz crystal as the system clock for the chipset. ? a 32.768 khz crystal for the real time clock and to refresh the dram in power down mode. ? optionally an external otp to disable the internal voice prompts, if preferred. ? a daa, user interface, microphone, loudspeaker, power supply, battery backup etc. telephone line interface tp 3054 codec analog winbond otp c host user interface display/key *option for external voice stamp on-chip voice prompt support /powerdown /reset 32.768 khz 24.576 mhz sysclk power/gnd testa, testb serial/parallel codec pio dram / flash (extport) system /dtsext /hostp8 16kx16 dts rom dts 4x1mx4 or 1x4mx4 dram 4 x 4 mbits flash 4 x 16 mbits flash dram or flash *host controls daa and front-end operation rtc timer dsp core dsp bus i/f hif figure 2. w62410 block diagram
preliminary w62410 - 4 - pin description power and clock pin name pin number i/o function v dd 10, 30, 50, 70, 87, 92 power gnd 20, 40, 60, 80, 88, 93 ground oscin 25 i 32768 hz crystal oscillator input oscop 26 o 32768 hz crystal oscillator output clkin 90 i 24.576 mhz crystal oscillator input clkop 91 o 24.576 mhz crystal oscillator output sysclk 100 o 24.576 mhz system clock output, while bit ensysclk in test reg. set, otherwise tri-state reset 83 i system hardware reset, internal pull high, schmitt trigger input pwdn 84 i power low indicator schmitt trigger input w/o pull high codec interface pin name pin number i/o function sclk 94 o serial clock at serial port, 2.048 mhz rfs 95 o receive frame sync. of serial port tfs 96 o transmit frame sync. of serial port dr 98 i serial data received at serial port dt 97 o serial data transmitted at serial port pio interface pin name pin number i/o function io 0..15 63, 64, 65, 66, 67, 68, 69, 71, 72, 73, 74, 7, 5, 76, 77, 78, 79 i/o bit i/o port internal pull-up as input
preliminary w62410 publication release date: april 2000 - 5 - revision a1 host interface pin name (parallel) pin name (serial) pin number i/o function hostp8 hostp8 81 i host selection input low for 8 bits parallel host mode high for serial host mode dack dack 27 o/p host acknowledge bytelh ------- 28 i/p parallel : select low or high byte d[0] hrdd 29 i/o parallel : bi-directional data bit 0 serial : host read data out d[1] hwrd 31 i/o parallel : bi- directional data bit 1 serial : host write data in hprd hrdclk 32 i/p parallel : read strobe in serial : host read clock in hpwr hwrclk 33 i/p parallel : read write in serial : host write clock in d[2..7] ------- 34, 35, 36, 37, 38, 39 i/o parallel : bi-directional data bit 2..7 dram/flash & extension port interface pin name (dram) i/o pin name (flash) i/o pin number description ras o eppo0 o 1 dram: row address strobe extport: extension parallel op 0 cas0 , 1, cas2 , 3 o epsio[0..3] i/o 2, 3, 4, 5 dram: column address strobe extport: extension serial io [0..3] with internal pull up mwr o epwr o 6 dram: dram write strobe extport: extension port write enable mrd o eprd o 7 dram: dram read strobe extport: extension port read enable ma[0..10] o eppo[1..7] epdata[4..7] o i/o 8, 9, 11, 12, 13, 1, 4, 15, 16, 17, 18, 19 dram: dram address bus extport: extension parallel op[1..7], extension bit data port[4..7]
preliminary w62410 - 6 - dram/flash & extension port interface, continued pin name (dram) i/o pin name (flash) i/o pin numbe r description ma[11] o irqex i 99 dram : dram address bit 11 extport: extension port interrupt md[0..3] i/o epdata[0..3] i/o 21, 22, 23, 24 dram: data bus for dram controller extport: extension bit data port[0..3] bi-directional i/o pin with repeater dts rom interface pin name pin number i/o function dtsext 82 i dts rom selection, internal pull-up 1: internal dts rom. in this mode the following 3 pins are of no use. 0: external dts rom wrp 62 o/p write clock pulse, active high rdp 61 o/p read clock pulse, active high otpdata 59 i/o bi-directional data line test p ins pin name pin number i/o function pllbypass 89 i pll bypass test mode for use in test machine only, internal pull up low : bypass pll, high : normal 4xf 58 o output, 4xclkin, while bit en4xf in test configuration reg. set to high, otherwise tri-state testa testb 86 85 i internal pull high , test mode set leave these pins nc in normal mode chipset bus interface: pin name pin number i/o function data[0..15] 41, 42, 43, 44, 45, 46, 47, 48, 49, 51, 52, 53, 54, 55, 56, 57 i/o test pins
preliminary w62410 publication release date: april 2000 - 7 - revision a1 booting sequence /reset nc or 11 test a,b booting codec interface ? the interface signals for the law codec are: sclk, rfs, tfs, dr and dt. ? the relationship between sysclk and sclk is as follows: () sclk sysclk sclkdiv = + 21 * () 1 5 * 2 000 , 576 , 24 048 , 2 + = mhz mhz ? therefore, the value of sclkdiv in the init command should be set to five when using the chipset with a sysclk of 24.576 mhz. this results in a sampling rate of 8 khz. the receive frame sync (rfs) rate hz hz 000 , 8 256 000 , 048 , 2 = .
preliminary w62410 - 8 - timeing waveforms codec timing sclk codec interface transmit timing tfs dt b7 b1 b0 2.048mhz 8khz triggered by writing tx reg sclk codec interface receive timing rfs dr b7 b6 b0 2.048mhz 8 khz h/w generated free running signal
preliminary w62410 publication release date: april 2000 - 9 - revision a1 dram as external storage memory selecting dram: the following t ypes of dram are allowed: type row column 1m 4 ma 0..9 ma 0..9 4m 4 ma 0..10 ma 0..10 4m 4 ma 0..11 ma 0..9 dram refresh: ? the dram controller uses c as- b efore- r as (cbr) in a distributed way at every 15.625 s. there are two different refresh modes available in the dram controller: normal mode: while in normal operation, the dram controller the refresh request is determined by the value of refdiv and of the sysclk. the exact formula can be found below: () s iod refreshper refdiv 625 . 15 1 * 576 . 24 1000 = = + thus, the refdiv value controls the refresh period. the default value is 383. 32768 mode: while in power down mode, the dram controller generates the refresh request at the frequency of 2 times 32,768 hz, or about every 15.3 s. por /reset refresh mode none normal 32768 normal reset run power down reset run operation condition refresh mode in different operation conditions enable dram
preliminary w62410 - 10 - dram normal read cycle /ras /cas sysclk ma row col t1 t2 t3 t4 t5 t6 t7 t8 t9 row md data latch in /mrd tcas /mwr dram early write cycle /ras /cas sysclk ma row col t1 t2 t3 t4 t5 t6 t7 t8 t9 row md /mrd /mwr dram normal cbr refresh cycle /ras /cas sysclk ma row t1 t2 t3 t4 t5 t6 t7 t8 t9 md /mrd high-z /mwr
preliminary w62410 publication release date: april 2000 - 11 - revision a1 dram cbr refresh cycle /ras /cas ma row md /mrd high-z /mwr /pwdnack flash as external storage memory flash interface (extension port) /eprd /epwr extension port mmp dmd[7..0] epdata[7..0] en dmaaddr /rd /wr enext eppo[7..0] d q epsio[3..0] d q en_sio irqex sync irq_ex enext and
preliminary w62410 - 12 - /eprd epdata[7..0] sysclk t0 t1 t2 t3 flash read cycle flash write cycle /epwr epdata[7..0] sysclk t0 t1 t2 t3 using flash with the w62410 w62410 km29n040t io[7..0] epdata[7..0] cle ale /re /we eppo[5..4] eppo[0] eppo[1] /ce /wp r/bn io[7..0] cle ale /re /we /ce /wp r/bn eppo[6] /epwr, /eprd irqex io[7..0] cle ale /re /we /ce /wp r/bn io[7..0] cle ale /re /we /ce /wp r/bn eppo[2] eppo[3] v r km29n040t km29n040t km29n040t km29n1600t km29n1600t km29n1600t km29n1600t dd
preliminary w62410 publication release date: april 2000 - 13 - revision a1 external otp functional waveform (for w55412 and w55412a) the w62410 has the capability to use an external otp instead of its own internal 256 kbits rom for the storage of voice prompts. below you can find the timing signals between the w62410 and either the w55412 or w55412a otp. note: a3, a2, a1, a0 is forced to low for word alignment. a[17..4] = dtsadd[13..0] wrp data rdp load dts data generate irq /wr dts status dtsadd add dtsdata data(add) irq_dtsrom a17 a16 a1 a0 1 2 17 18 12 16 d0 d1 d15 12 16 d0 d1 d15 /rd dts data drdy endts add+1 min 1 s host interface (hif) the w62410 allows connecting to the host controller through a serial or a 8 bits parallel (8051- like) port. the port is selected through the /hostp8pin: /hostp8pin selects low 8-bit parallel (8051-like) interface high serial controller interface
preliminary w62410 - 14 - 8-bits controller interface controller lhsq4808a /bytelh /dack d[0..7] /rd, /wr /hostp8 gnd 8-bit parallel interface /bytelh d[0..7] /rd data data /wr low byte high byte 8-bit parallel data transfer ? the controller can send a command to the w62410 by writing the low byte first followed by the high byte of the 16-bit command word. ? the controller can read the 16-bit result from the w62410 by reading the low byte first followed by the high byte after receiving a /dack interrupt from the w62410 to indicate that there is data to be read. serial controller interface controller lhsq4808a hwrd hwrclk hrdd /hostp8 vdd /dack hrdclk serial port
preliminary w62410 publication release date: april 2000 - 15 - revision a1 the host can write a 16-bit command in the following way: ? check that the /dack pin is set high to be sure you can send a new command to the w62410. ? the controller has to toggle hwrclk and hwrd to send the 16-bit command to the command register of the w62410. the w62410 samples in the hwrd, with lsb first, at the falling edge of hwrclk. after having received 16 falling edges, the hwrclk returns to low and the complete 16-bit command has been stored in the command register of the w62410. ? the hif asserts comrdy and generates an irq_host inside the w62410. after the w62410 has read the 16-bit command, the comrdy signal will return to the low state. serial host interface timing host write, hwrclk normal low hwrclk hwrd d0 d14 d13 d15 irq_host dsp rd comrdy d1 /dack the host can read the 16-bit result in the following way: ? when the w62410 writes into the result register, then the dack pin will be set low. ? the ?controller has to toggle the hrdclk to sample the hrdd. the ?controller will receive the 16- bit data with lsb first on the hrdd pin, at the falling edge of hrdclk. after 16 falling edges the complete result has been received, hrdclk returns to low and the dack pin will be set high again. serial host interface timing host read, hrdclk in normal low hrdclk hrdd d15 d14 d1 d0 /dack dsp wr response irq_host ** note * : hi-z
preliminary w62410 - 16 - pio controller d15 r vdd din dout dmd io port configuration pwdn pio 15 ? the i/o ports of io 0..15 are bi-directional. ? if user read the i/o port, the output latch will stay in tri-state mode and a weak pull high of about 40 a will be present to have data input. ? for the transition from write to read state, a dummy read is needed. ? the i/o port will stay in output tri-state condition (including the pull high) during power down mode and the input will be gated to avoid leakage current. power on reset and h/w reset ? the tad provides an internal power on reset while power building up for the very first time (this is a different situation than resetting the w62410 after putting the w62410 in power down mode). the power on reset signal will force the real time clock to be set to zero. ? to ensure that the system crystal oscillate properly, the reset signal must be kept low for at least 200 ms. this reset signal will not affect the memory nor the real time clock value. power down mode ? operation current idd < 80 ma at 5v ? idle mode idd < 40 ma at 5v ? power down mode < 100 a at 5v ? a low signal on the pwdn pin will invoke the highest priority interrupt vector to wake up the w62410. ? during power down, the system clock oscillating at 24.576 mhz, is stopped, except the real time clock and dram refresh. the 32768 hz oscillator will take over to support the real time clock and the dram refresh control signals. ? the input/output pins will be kept in tri-state mode to isolate the dc path in power down mode. ? after pwdn release, a hardware reset signal must be activated again to let the w62410 wakeup and restart.
preliminary w62410 publication release date: april 2000 - 17 - revision a1 ? in case of the use of flash as external storage memory, power can be removed totally. the 32768 oscillator may be unnecessary, if controller can maintain the real time clock itself or is deemed unnecessary for the application. power-up reset, power-down, external h/w reset internal h/w reset /reset reset logic /pwdn power on reset irq_pwdn to interrupt controller vdd r power down for dram configuration vdd /reset por /pwdn power down for flash configuration vdd /reset por /pwdn
preliminary w62410 - 18 - master crystal oscillator circuit (24.576 mhz) 2200 ohm 24.567 mhz 20p 20p clkin (90) clkop (91) 5 v 100 kohm 10 uf 2sa1015 real time clock oscillator circuit (32768 hz) 1000 ohm 32768 hz 10p 10p oscin (25) oscop (26)
preliminary w62410 publication release date: april 2000 - 19 - revision a1 absolute maximum ratings parameter symbol min. max. unit dc power supply v dd ? v ss -0.3 +7.0 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t a 0 70 c storage temperature t st -55 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device. electrical characteristics dc characteristics (v dd ? vss = 5v 10%, t a = 25 , clkin = 24.576 mhz, oscin = 32768 hz) parameter sym. conditions limits unit min. typ. max. operating voltage v dd - 4.5 5.0 5.5 v operating current i dd - 90 ma power down current i pwd power down mode - 900 a i lk1 all except pull high or low, tri-state, irqex -10 +10 input leakage current i lk2 internal pull high pin they are reset , pllbypass , testa, testb, -300 +10 a i lk3 irqex -200 +100 output voltage low v ol iol = 8 ma - 0.45 v output voltage high v oh ioh = -8 ma 2.4 - input voltage low v il all except reset , pwdn , osc, clk pin - 0.8 v input voltage high v ih all except reset , pwdn , osc, clk pin 2.0 - input voltage low v ils reset , pwdn pin, schmitt trigger input - 0.8 v input voltage high v ihs reset , pwdn pin, schmitt trigger input 2.4 - input voltage low v ilx oscin, clkin pin, xtal oscillator input - 1.5 v input voltage high v ihx oscin, clkin pin, xtal oscillator input 3.5 -
preliminary w62410 - 20 - package dimensions 100l qfp(14 x 20 x 2.75 mm footprint 4.8 mm) e h y a a2 seating plane l l 1 see detail f controlling dimension: millimeters a1 e d h d eb c 0.08 0 7 0 0.003 2.40 1.40 19.20 1.20 18.80 1.00 18.40 0.064 0.055 0.992 0.756 0.047 0.976 0.740 0.039 0.960 0.746 0.65 20.10 14.10 0.20 0.40 2.87 20.00 14.00 2.72 19.90 13.90 0.10 0.20 2.57 0.791 0.555 0.008 0.016 0.113 0.787 0.551 0.107 0.026 0.783 0.547 0.004 0.008 0.101 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.012 0.006 0.15 0.30 24.40 24.80 25.20 7 0.020 0.032 0.498 0.802 0.35 0.25 0.010 0.014 0.018 0.45
preliminary w62410 publication release date: april 2000 - 21 - revision a1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3- 5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-271 97006 taipei office 11f, no. 115, sec. 3, min -sheng east rd., taipei, taiwan tel: 886-2- 27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. unit 9-15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852-2 7513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change withou t notice. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3- 5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-271 97006 taipei office 11f, no. 115, sec. 3, min -sheng east rd., taipei, taiwan tel: 886-2- 27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. unit 9-15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852-2 7513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change withou t notice.

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